1
views
0
recommends
+1 Recommend
0 collections
    0
    shares
      • Record: found
      • Abstract: not found
      • Article: not found

      Nanoscale imaging of mobile carriers and trapped charges in delta doped silicon p–n junctions

      Read this article at

      ScienceOpenPublisher
      Bookmark
          There is no author summary for this article yet. Authors can add summaries to their articles on ScienceOpen to make them more accessible to a non-specialist audience.

          Related collections

          Most cited references40

          • Record: found
          • Abstract: not found
          • Article: not found

          Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties

            Bookmark
            • Record: found
            • Abstract: found
            • Article: not found

            High-resolution non-destructive three-dimensional imaging of integrated circuits

            Modern nanoelectronics has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques. Foreseeable developments in X-ray sources, optics and detectors, as well as adoption of an instrument geometry optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.
              Bookmark
              • Record: found
              • Abstract: not found
              • Article: not found

              Description of the SiO2Si interface properties by means of very low frequency MOS capacitance measurements

                Bookmark

                Author and article information

                Contributors
                (View ORCID Profile)
                (View ORCID Profile)
                (View ORCID Profile)
                (View ORCID Profile)
                Journal
                Nature Electronics
                Nat Electron
                Springer Science and Business Media LLC
                2520-1131
                July 27 2020
                Article
                10.1038/s41928-020-0450-8
                e81a1f26-d8d6-4be7-a255-d4bdd8498ddc
                © 2020

                http://www.springer.com/tdm

                http://www.springer.com/tdm

                History

                Comments

                Comment on this article