B-Doped δ-Layers and Nanowires from Area-Selective Deposition of BCl ₃ on Si(100)

As silicon electronics approaches the atomic scale, interconnects and circuitry become comparable in size to the active device components. Maintaining low electrical resistivity at this scale is challenging because of the presence of confining surfaces and interfaces. We report on the fabrication of wires in silicon--only one atom tall and four atoms wide--with exceptionally low resistivity (~0.3 milliohm-centimeters) and the current-carrying capabilities of copper. By embedding phosphorus atoms within a silicon crystal with an average spacing of less than 1 nanometer, we achieved a diameter-independent resistivity, which demonstrates ohmic scaling to the atomic limit. Atomistic tight-binding calculations confirm the metallicity of these atomic-scale wires, which pave the way for single-atom device architectures for both classical and quantum information processing.

Bottom-up nanofabrication by area-selective atomic layer deposition (ALD) is currently gaining momentum in semiconductor processing, because of the increasing need for eliminating the edge placement errors of top-down processing. Moreover, area-selective ALD offers new opportunities in many other areas such as the synthesis of catalysts with atomic-level control. This Perspective provides an overview of the current developments in the field of area-selective ALD, discusses the challenge of achieving a high selectivity, and provides a vision for how area-selective ALD processes can be improved. A general cause for the loss of selectivity during deposition is that the character of surfaces on which no deposition should take place changes when it is exposed to the ALD chemistry. A solution is to implement correction steps during ALD involving for example surface functionalization or selective etching. This leads to the development of advanced ALD cycles by combining conventional two-step ALD cycles with correction steps in multistep cycle and/or supercycle recipes.