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      RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults

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          Abstract

          To maximize the performance and energy efficiency of Spiking Neural Network (SNN) processing on resource-constrained embedded systems, specialized hardware accelerators/chips are employed. However, these SNN chips may suffer from permanent faults which can affect the functionality of weight memory and neuron behavior, thereby causing potentially significant accuracy degradation and system malfunctioning. Such permanent faults may come from manufacturing defects during the fabrication process, and/or from device/transistor damages (e.g., due to wear out) during the run-time operation. However, the impact of permanent faults in SNN chips and the respective mitigation techniques have not been thoroughly investigated yet. Toward this, we propose RescueSNN, a novel methodology to mitigate permanent faults in the compute engine of SNN chips without requiring additional retraining, thereby significantly cutting down the design time and retraining costs, while maintaining the throughput and quality. The key ideas of our RescueSNN methodology are (1) analyzing the characteristics of SNN under permanent faults; (2) leveraging this analysis to improve the SNN fault-tolerance through effective fault-aware mapping (FAM); and (3) devising lightweight hardware enhancements to support FAM. Our FAM technique leverages the fault map of SNN compute engine for (i) minimizing weight corruption when mapping weight bits on the faulty memory cells, and (ii) selectively employing faulty neurons that do not cause significant accuracy degradation to maintain accuracy and throughput, while considering the SNN operations and processing dataflow. The experimental results show that our RescueSNN improves accuracy by up to 80% while maintaining the throughput reduction below 25% in high fault rate (e.g., 0.5 of the potential fault locations), as compared to running SNNs on the faulty chip without mitigation. In this manner, the embedded systems that employ RescueSNN-enhanced chips can efficiently ensure reliable executions against permanent faults during their operational lifetime.

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          Which model to use for cortical spiking neurons?

          We discuss the biological plausibility and computational efficiency of some of the most useful models of spiking and bursting neurons. We compare their applicability to large-scale simulations of cortical neural networks.
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                Author and article information

                Contributors
                Journal
                Front Neurosci
                Front Neurosci
                Front. Neurosci.
                Frontiers in Neuroscience
                Frontiers Media S.A.
                1662-4548
                1662-453X
                12 April 2023
                2023
                : 17
                : 1159440
                Affiliations
                [1] 1Embedded Computing Systems, Institute of Computer Engineering, Technische Universität Wien (TU Wien) , Vienna, Austria
                [2] 2eBrain Lab, Division of Engineering, New York University Abu Dhabi (NYUAD) , Abu Dhabi, United Arab Emirates
                Author notes

                Edited by: Joon Young Kwak, Korea Institute of Science and Technology (KIST), Republic of Korea

                Reviewed by: Beomseok Kang, Georgia Institute of Technology, United States; Tuo Shi, Zhejiang Lab, China

                *Correspondence: Rachmad Vidya Wicaksana Putra rachmad.putra@ 123456tuwien.ac.at

                This article was submitted to Neuromorphic Engineering, a section of the journal Frontiers in Neuroscience

                Article
                10.3389/fnins.2023.1159440
                10130579
                e6817f22-5461-4537-82f8-6fa50c518842
                Copyright © 2023 Putra, Hanif and Shafique.

                This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) and the copyright owner(s) are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.

                History
                : 05 February 2023
                : 24 March 2023
                Page count
                Figures: 15, Tables: 0, Equations: 1, References: 50, Pages: 17, Words: 9203
                Funding
                This work was supported in parts by the Center for Artificial Intelligence and Robotics (CAIR), funded by Tamkeen under the NYUAD Research Institute Award CG010, and the Center for Cyber Security (CCS), funded by Tamkeen under the NYUAD Research Institute Award G1104. This work was also partially supported by the project “eDLAuto: An Automated Framework for Energy-Efficient Embedded Deep Learning in Autonomous Systems”, funded by the NYUAD Research Enhancement Fund (REF). The authors acknowledge TU Wien Bibliothek for the publication fee support through its Open Access Funding Program.
                Categories
                Neuroscience
                Original Research

                Neurosciences
                spiking neural networks,accelerators,fault tolerance,manufacturing defects,reliability,resilience,permanent faults

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