Influence of Ta/Si atomic ratio on the interdiffusion between Ta–Si–N and Cu at elevated temperature

The Semiconductor Industry Association (SIA) roadmap calls for the incorporation of Cu plugs (vias) integrated with interconnects in 1997. Copper is being evaluated for ULSI metallization because of its lower bulk electrical resistivity and its superior resistance to electromigration and stress voiding as compared to commonly used aluminum and its alloys. One of the major drawbacks of Cu is its fast diffusion in Si and drift in SiO2-based dielectrics, resulting in the deterioration of devices at low temperatures. Hence a diffusion barrier is necessary between Cu and Si or SiO2. Figure 1 is a cross section of a three metal level interconnect structure using Cu as the conductive material. The interlevel dielectrics (ILD) could be conventional SiO2-based materials or more ideally, materials with low dielectric constants such as polyimide. If conventional SiO2is used, then Cu plugs and interconnects have to be enclosed in diffusion/drift barriers so that Cu will not move into Si or SiO2under thermal stress or biased temperature stress (BTS). This article reviews the published studies on conductive diffusion barriers between thin Cu films and Si substrates. In addition, the work on diffusion and drift of Cu into commonly used inorganic dielectric systems is also summarized. Finally, some concerns involving diffusion/drift barriers between Cu and Si or SiO2for sub-0.5 μm feature size with high aspect ratios are discussed.