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      MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications

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          A family of VLSI designs for the motion compensation block-matching algorithm

          M.-T. Sun, L. Wu, K-M Yang (1989)
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            Design of a Massively Parallel Processor

            Batcher (1980)
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              FPGA and CPLD architectures: a tutorial

              S. Brown, J. Rose (1997)
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                Author and article information

                Journal
                Title: IEEE Transactions on Computers
                Abbreviated Title: IEEE Trans. Comput.
                Publisher: Institute of Electrical and Electronics Engineers (IEEE)
                ISSN (Print): 00189340
                Publication date (Print): May 2000
                Volume: 49
                Issue: 5
                Pages: 465-481
                Article
                DOI: 10.1109/12.859540
                SO-VID: a3c22c45-c26f-4843-bdd9-6e0fa882f1d3
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