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Logical modelling of delay degradation effect in static CMOS gates
Author(s):
M.J. Bellido-Díaz
,
J. Juan-Chico
,
A.J. Acosta
,
M. VALENCIA
,
J.L. Huertas
,
M. N. Bellido
,
T. Chico
,
AJ Acosta-Rua
,
M. Valencia
,
JL Huertas
,
MJ Meneu-Diaz
Publication date:
2000
Journal:
IEE Proceedings - Circuits, Devices and Systems
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DOI::
10.1049/ip-cds:20000197
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