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Logical modelling of delay degradation effect in static CMOS gates
M.J. Bellido-Díaz, J. Juan-Chico, A.J. Acosta, M. VALENCIA, J.L. Huertas, M. N. Bellido, T. Chico, AJ Acosta-Rua, M. Valencia, JL Huertas, MJ Meneu-Diaz
2000
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