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      A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

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          A filtering technique to lower LC oscillator phase noise

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            All-digital PLL and transmitter for mobile phones

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              1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

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                Author and article information

                Journal
                IEEE Journal of Solid-State Circuits
                IEEE J. Solid-State Circuits
                Institute of Electrical and Electronics Engineers (IEEE)
                0018-9200
                December 2008
                December 2008
                : 43
                : 12
                : 2776-2786
                Article
                10.1109/JSSC.2008.2005704
                4abd83bb-aba7-4ab8-b66f-1d97b75c570d
                © 2008
                History

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