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      fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library

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          Abstract

          Machine learning ensembles combine multiple base models to produce a more accurate output. They can be applied to a range of machine learning problems, including anomaly detection. In this paper, we investigate how to maximize the composability and scalability of an FPGA-based streaming ensemble anomaly detector (fSEAD). To achieve this, we propose a flexible computing architecture consisting of multiple partially reconfigurable regions, pblocks, which each implement anomaly detectors. Our proof-of-concept design supports three state-of-the-art anomaly detection algorithms: Loda, RS-Hash and xStream. Each algorithm is scalable, meaning multiple instances can be placed within a pblock to improve performance. Moreover, fSEAD is implemented using High-level synthesis (HLS), meaning further custom anomaly detectors can be supported. Pblocks are interconnected via an AXI-switch, enabling them to be composed in an arbitrary fashion before combining and merging results at run-time to create an ensemble that maximizes the use of FPGA resources and accuracy. Through utilizing reconfigurable Dynamic Function eXchange (DFX), the detector can be modified at run-time to adapt to changing environmental conditions. We compare fSEAD to an equivalent central processing unit (CPU) implementation using four standard datasets, with speed-ups ranging from 3× to 8×.

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          Author and article information

          Journal
          09 June 2024
          Article
          10.1145/3568992
          2406.05999
          1eea6f40-8c99-4817-8564-7861dce006f2

          http://arxiv.org/licenses/nonexclusive-distrib/1.0/

          History
          Custom metadata
          ACM Transactions on Reconfigurable Technology and Systems(TRETS),16, 3, Article 42 (2023). Journal Track of The International Conference on Field Programmable Technology (FPT'22), Hong Kong SAR, China
          The source code for this paper is available at: https://github.com/bingleilou/fSEAD
          cs.AR cs.AI cs.LG

          Artificial intelligence,Hardware architecture
          Artificial intelligence, Hardware architecture

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